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PRELIMINARY TECHNICAL DATA
a
Preliminary Technical Data
FEATURES 16-bit Resolution AD5543 14-btt Resolution AD5553 1 LSB DNL 1, 2 or 4 LSB INL 2mA Full Scale Current 20%, with VREF=10V 0.5s Settling Time 4Q Multiplying Reference-input 3-Wire Interface Ultra Compact uSOIC-8 Package APPLICATIONS Automatic Test Equipment Instrumentation Digitally Controlled Calibration Industrial Control PLCs
GENERAL DESCRIPTION The AD5543, 16-bit, current-output, digital-to-analog converter is designed to operate from a single +5 volt supply. The applied external reference input voltage VREF determines the full-scale output-current. An internal feedback resistor (RFB) provides temperature tracking for the full-scale output when combined with an external I to V precision amplifier. A serial-data interface offers high-speed, three-wire micro controller compatible inputs using serial-data-in (SDI), clock (CLK), and (CS/LD). The AD5543/AD5553 are packaged in the space saving SO-8, and the ultra compact (3x4.7mm) uSOIC-8.
Current-Output Serial-Input, 16-/14-Bit DAC
AD5543/AD5553
RFB
FUNCTIONAL DIAGRAMS
AD5543 / AD5553
D/A CONVERTER 16 OR 14 CS/LD DAC REGISTER 16 OR 14 CLK SDI 16-/14-BIT SHIFT REGISTER GND
VDD VREF
IOUT
ORDERING GUIDE
MODEL AD5543CR AD5543BR AD5543BRM AD5553CRM INL (LSB) 1 2 2 1 RES (LSB) 16 16 16 14 TEMP RANGE Package Description Package Option R-8 R-8 RM-8 RM-8
Figure 1. Integral Nonlinearity Error Plot
-40 / +85C SO-8 -40 / +85C SO-8 -40 / +85C uSOIC-8 -40 / +85C uSOIC-8
The AD5543 contains xxxx transistors. The die size measures 53 mil X 73 mil, 3,879 sqmil.
REV. PrJ 19 FEB `2002 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 Fax: 781/326-8703 www.analog.com (c)Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
AD5543/AD5553
ELECTRICAL CHARACTERISTICS at VDD = 5V10%, VSS = 0V, IOUT = Virtual GND, GND=0V, VREF = 10V, TA = Full Operating temperature
Range, unless otherwise noted. PARAMETER SYMBOL STATIC PERFORMANCE1 Resolution N Resolution N Relative Accuracy INL Relative Accuracy INL Differential Nonlinearity DNL Output Leakage Current IOUT Output Leakage Current IOUT Full-Scale Gain Error GFSE Full-Scale Tempco2 TCVFS REFERENCE INPUT VREF Range VREF Input Resistance RREF Input Capacitance2 CREF ANALOG OUTPUT Output Current IOUT Output Capacitance2 COUT LOGIC INPUTS & OUTPUT Logic Input Low Voltage VIL Logic Input High Voltage VIH Input Leakage Current IIL Input Capacitance2 CIL 2, 3 INTERFACE TIMING Clock Input Frequency fCLK Clock Width High tCH Clock Width Low tCL CS to Clock Set Up tCSS Clock to CS Hold tCSH Data Setup tDS Data Hold tDH SUPPLY CHARACTERISTICS Power Supply Range VDD RANGE Positive Supply Current IDD Power Dissipation PDISS Power Supply Sensitivity PSS NOTES:
1. 2. 3. 4. All static performance tests (except IOUT) are performed in a closed loop system using an external precision OP177 I-to-V converter amplifier. The AD5543 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25C These parameters are guaranteed by design and not subject to production testing. All input control signals are specified with tR = tF = 2.5ns (10% to 90% of +3V) and timed from a voltage level of 1.5V. All AC Characteristic tests are performed in a closed loop system using an OP42 I-to-V converter amplifier.
CONDITION 1 LSB = VREF/216 = 153V when VREF = 10V AD5543 1 LSB = VREF/214 = 610V when VREF = 10V AD5553 Grade: AD5543C, AD5553C Grade: AD5543B Monotonic Data = 0000H, TA = 25C Data = 0000H, TA = TA MAX Data = FFFFH
5V10% 16 14 1 2 1 10 20 1/4 1 -15/+15 5 5
UNITS Bits Bits LSB max LSB max LSB max nA max nA max
mV typ/max
ppm/C typ V min/max k ohm typ4 pF typ mA typ pF typ V max V min A max pF max MHz ns min ns min ns min ns min ns min ns min V min/max A max mW max %/% max
Data = FFFFH Code Dependent
2 200 0.8 2.4 10 10 40 10 10 0 10 5 10 4.5/5.5 10 0.055 0.006
Logic Inputs = 0V Logic Inputs = 0V VDD = 5%
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PRELIMINARY TECHNICAL DATA
AD5543/AD5553
ELECTRICAL CHARACTERISTICS at VDD = 5V10%, IOUT = Virtual GND, GND=0V, VREF = 10V,
TA = Full Operating Temperature Range, unless otherwise noted. PARAMETER AC CHARACTERISTICS Output Voltage Settling Time Reference Multiplying BW DAC Glitch Impulse Feed Through Error Digital Feed Through Total Harmonic Distortion Output Spot Noise Voltage NOTES:
1. 2. 3. 4.
SYMBOL tS BW Q VOUT/VREF Q THD eN
CONDITION To 0.1% of Full Scale, Data = 0000H to FFFFH to 0000H VREF = 5VP-P, Data = FFFFH VREF = 0V, Data 0000H to 8000H to 0000H Data = 0000H, VREF = 100mVrms, same channel CS = 1, and fCLK = 1MHz VREF = 5VP-P, Data = FFFFH, f=1KHz f = 1kHz, BW = 1Hz
5V10% 0.5 4 7 -65 7 -73 4
UNITS s typ MHz typ nV-s typ dB nV-s typ dB typ nV/ rt Hz
All static performance tests (except IOUT) are performed in a closed loop system using an external precision OP177 I-to-V converter amplifier. The AD5543 RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25C These parameters are guaranteed by design and not subject to production testing. All input control signals are specified with tR = tF = 2.5ns (10% to 90% of +3V) and timed from a voltage level of 1.5V. All AC Characteristic tests are performed in a closed loop system using an OP42 I-to-V converter amplifier.
ABSOLUTE MAXIMUM RATINGS
VDD to GND .............................................................. -0.3V, +8V VREF to GND ...............................................................-18V, 18V Logic Inputs to GND................................................. -0.3V, +8V V(IOUT) to GND ...........................................-0.3V, VDD + 0.3V Input Current to Any Pin except Supplies........................ 50mA Package Power Dissipation .................... (TJ MAX - TA)/ THETAJA Thermal Resistance THETAJA 8-lead Surface Mount (SO-8).................................. 100C/W Maximum Junction Temperature (TJ MAX) ........................ 150C Operating Temperature Range Models A, B, C ................................................-40C to +85C Storage Temperature Range ..............................-65C to +150C Lead Temperature: R-8, RM-8 (Vapor Phase, 60 secs)............................. +215C R-8, RM-8 (Infrared, 15 secs) .................................... +220C
Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 2. Reference Multiplying Bandwidth
PIN CONFIGURATION
CLK SDI RFB VREF
1 2 3 4 8 CS
AD5543 AD5553
7 VDD 6 GND 5 IOUT
Figure 3. Settling time
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PRELIMINARY TECHNICAL DATA
AD5543/AD5553
SDI CLK tDS t CSS CS tDH tCH tCL tCSH
D15 D14 D13 D12 D11 D10 D9 D8 D1 D0
Figure 2. Timing Diagram
Table 1. Control-Logic Truth Table
CLK CS
X + X X H L H +
Serial Shift Register Function
No Effect Shift-Register-Data advanced one bit No Effect Shift-Register-Data transferred to DAC Register
DAC Register
Latched Latched Latched New Data loaded from Serial Register
Notes: 1. + positive logic transition; X Don't Care Table 2. AD5543 Serial Input Register Data Format; Data is loaded in the MSB-First Format. MSB LSB Bit Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 3. AD5553 Serial Input Register Data Format; Data is loaded in the MSB-First Format. MSB LSB Bit Position B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A full 16-bit data word can be loaded into the DAC serial input register, but only the last 14-bits entered will be transferred to the DAC register when CS returns to logic high.
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PRELIMINARY TECHNICAL DATA
AD5543/AD5553
PIN DESCRIPTION
PIN# Name 1 2 CLK SDI Function Clock input, positive-edge triggered clocks data into shift register. Serial Register Input, data loads directly into the shift register MSB first. Extra leading bits are ignored. Internal matching Feedback Resistor. Connect to external opamp output. 5 6 7 8 IOUT GND VDD CS 4 VREF DAC reference input pin. Establishes DAC full-scale voltage. Constant input resistance versus code. DAC current-output. Connects to inverting terminal of external precision I to V opamp Analog & Digital Ground. Positive power supply input. Specified range of operation +5V 10%. Chip Select, active low digital input. Transfers shift-register data to DAC register on rising edge. See truth table for operation.
3
RFB
CIRCUIT OPERATION
The AD5543/AD5553 contains a 16-/14-bit, current-output, digital-to-analog converter, a serial input register, and a DAC register. Both parts use a 3-wire serial data interface. D/A Converter Section The DAC architecture uses a current-steering R-2R ladder design. Figure 3 shows the typical equivalent DAC. The DAC contains a matching feedback resistor for use with an external I to V converter amplifier. The RFB pin is connected to the output of the external amplifier. The IOUT terminal is connected to the inverting input of the external amplifier. These DACs are designed to operate with both negative or positive reference voltages. The VDD power pin is only used by the logic to drive the DAC switches ON and OFF. Note that a matching switch is used in series with the internal 5K-ohm feedback resistor. If users are attempting to measure the value of RFB, power must be applied to VDD in order to achieve continuity. The VREF input voltage and the digital data (D) loaded into the corresponding DAC register according to equation [1 &2] determines the DAC output voltage: VOUT = -VREF * D / 65,536 VOUT = -VREF * D / 16,384 Equation 1 Equation 2
R VREF 5K 2R 2R 2R R R R
VDD RFB
S2
S1 IOUT
GND
DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY SWITCHES S1 & S2 ARE CLOSED, VDD MUST BE POWERED
Figure 3. Equivalent R-2R DAC Circuit These DACs are also designed to accommodate AC reference input signals. The AD5543 will accommodate input reference voltages in the range of -12 to +12 volts. The reference voltage inputs exhibit a constant nominal input-resistance value of 5K ohms, 30%. The DAC output (IOUT) is code-dependent producing various output resistances and capacitances. External amplifier choice should take into account the variation in impedance generated by the AD5543 on the amplifiers inverting input node. The feedback resistance in parallel with the DAC ladder resistance dominates output voltage noise. In order to maintain good analog performance, power supply bypassing of 0.01uF in parallel with 1uF is recommended. Under these conditions clean power supply voltages (low ripple, avoid switching supplies) appropriate for the application should be used. It is best to derive the AD5543's +5V supply from the systems analog supply voltages. (Don't use the digital 5V supply). See figure 4.
Note that the output full-scale polarity is opposite to the VREF polarity for DC reference voltages.
VIN +10.000V VOUT AD587
+15V ANALOG POWER SUPPLY 2R +5V VDD AD5543 5K R GND R RFB R
R VREF 2R 2R
R 2R
+15V S1 IOUT VOUT VCC
S2
A1
LOAD VEE
GND DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY SWITCHES S1 & S2 ARE CLOSED, VDD MUST BE POWERED
Figure 4. Recommended System Connections
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PRELIMINARY TECHNICAL DATA
AD5543/AD5553
SERIAL DATA INTERFACE The AD5543 uses a 3-wire (CS/LD, SDI, CLK) serial data interface. New serial data is clocked into the serial input register in a 16-bit data-word format. The MSB bit is loaded first. Table 2 defines the 16 data-word bits. Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data setup and data hold time requirements specified in the INTERFACE TIMING SPECIFICATIONS. Only the last 16-bits clocked into the serial register will be interrogated when the CS pin is strobed to transfer the serial register data to the DAC register. Since most micro controllers' output serial data in 8-bit bytes, two right justified data bytes can be written to the AD5543. After loading the serial register the rising edge of CS transfers the serial register data to the DAC register, during this strobe the CLK should not be toggled. ESD Protection Circuits All logic-input pins contain back-biased ESD protection Zeners connected to ground (GND) and VDD as shown in figure 7.
VDD DIGITAL INPUTS 5K DGND
is easily accomplished using an additional external amplifier (A2) configured as a summing amplifier, see figure 8. In this circuit the second amplifier (A2) provides a gain of 2 which increases the output span magnitude to 20 volts. Biasing the external amplifier with a 10V offset from the reference voltage results in a full 4-quadrant multiplying circuit. The transfer equation of this circuit shows that both negative and positive output voltages are created as the input data (D) is incremented from code zero (VOUT = -10V) to midscale (VOUT = 0V) to fullscale (VOUT = +10V). VOUT = (D / 32768 - 1) * VREF
10K 10K +10V 5K VREF AD588 GND VDD A2 -10V < VOUT < +10V VOUT
Equation 3
VREF
RFB IOUT
AD5543 A1 GND GND
DIGITAL INTERFAC CONNECTIONS OMITTED FOR CLAR E ITY
Figure 8. Four-Quadrant Multiplying Application Circuit PCB Layout Recommendations A star ground approach should be used as shown in figure 8. The PCB metal traces between VREF and RFB should match in order to minimize gain error.
Figure 7. Equivalent ESD Protection Circuits APPLICATIONS The AD5543 is inherently a 2-Quadrant multiplying D/A converter. That is, it can be easily set up for Unipolar output operation. The full-scale output polarity is the inverse of the reference-input voltage. In some applications it may be necessary to generate the full 4Quadrant multiplying capability or a bipolar output swing. This
Mechanical Outline Dimensions
Dimensions shown in inches and (mm).
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